Description: 4 digital LED dynamic display的Verilog HDL源代码，它能动态的显示4位数，为FPGA 的DEBUG 提供便利，非常经典，简单易懂，并且经过了Modelsim/ISE/FPGA(XC3S250ETQ144)验证和实现，好的行为模型就应该大家分享。-4 digital LED dynamic display of the Verilog HDL source code, it can dynamically display 4-digit for the FPGA to facilitate the DEBUG, very classic, easy-to-read, and after Modelsim/ISE/FPGA (XC3S250ETQ144) authentication and realize, good The behavior model should be shared. Platform: |
Size: 257024 |
Author:name |
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Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing. Platform: |
Size: 9216 |
Author:李乔 |
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Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform. Platform: |
Size: 471040 |
Author:郭先生 |
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Description: This document serves as an example based tutorial to programming the Spartan 3 FPGA included in your parts kit using Xilinx ISE Tools. A Basic working knowledge of how to create schematics in Xilinx is required.
The Spartan 3 FPGA can be programming directly from the Xilinx ISE package, greatly simplifying and expediting the design process. Programming the FPGA using a schematic, state diagram, or verilog module is a universally simple and straightforward process. Platform: |
Size: 253952 |
Author:Mohamed Saleh |
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Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE, Platform: |
Size: 2891776 |
Author:蜡笔 |
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Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC
cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of
codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device
for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is
implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC
code． Platform: |
Size: 165888 |
Author:秦小星 |
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Description: CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA Platform: |
Size: 863232 |
Author:张小琛 |
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Description: 备注：使用的是VeriLog HDL语言
软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e .
功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read. Platform: |
Size: 5120 |
Author:李钿 |
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Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5 Platform: |
Size: 2594816 |
Author:linzi |
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Description: Xilinx公司推荐FPGA培
训教材Xilinx ISE 9.xFPGA/CPLD设计指南的配套光盘内容，每个程序含verilog和VHDL两具版本-Training materials recommended by Xilinx Xilinx ISE 9.xFPGA/CPLD FPGA design guidelines supporting the CD content, each program contains two versions of verilog and VHDL Platform: |
Size: 8774656 |
Author:王建伟 |
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Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT. Platform: |
Size: 56320 |
Author:zzy |
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Description: 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware description language Verilog, ISE on the complete software development platform, can be compared with high-speed clock frequency (48MHz) to work properly. The digital frequency meter using frequency measurement method, can accurately measure the frequency of the signal between 10Hz to 100MHz. Platform: |
Size: 1880064 |
Author:PengJ |
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Description: 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。
2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-clock with Verilog HDL CPU controller, the ISE on the waveform simulation and FPGA implementation. Platform: |
Size: 1024 |
Author:dino |
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Description: ofdm系统完整源代码，verilog语言编写，在ise平台测试通过-ofdm source code in verilog, run in ise fpga platform Platform: |
Size: 3791872 |
Author:CloudZhang |
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Description: 文件中为lms算法的ise工程，其中包含了lms算法的fpga实现的verilog程序以及testbench，很好的在FPGA上实现了lms算法，还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger summary Platform: |
Size: 2805760 |
Author:黄远望 |
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Description: 利用FPGA模拟弹钢琴的Verilog代码。在Xilinx ISE 14.3 编译通过-Using FPGA Verilog code simulation play the piano. Compiled by Xilinx ISE 14.3 Platform: |
Size: 1278976 |
Author:侯松岩 |
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Description: 基于FPGA设计I2C总线，使用Verilog语言，ISE环境，含有仿真结果-I2C bus based on FPGA design using Verilog language, ISE environment containing simulation results Platform: |
Size: 178176 |
Author:huangyu |
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